In recent years, the capacity of a non-volatile semiconductor storage device that is represented by a flash memory has remarkably increased, and it is announced that a product having the capacity of about 32 GB is released. The non-volatile semiconductor storage device is increasing in a commodity value, particularly as a USB memory or a storage device for a mobile phone. In addition, principled superiority of the non-volatile semiconductor storage device such as vibration resistance, high reliability, and low power consumption implemented by only a solid-state element memory attracts attention, and thus the non-volatile semiconductor storage device becomes a mainstream storage device for a portable electronic apparatus, such as a storage device for a portable music player to reproduce music and an image.
Meanwhile, separately from an application for the storage device, realization of the same performance as that of a Dynamic Random Access Memory (DRAM) currently used as a main memory of an information apparatus in the non-volatile semiconductor storage device is actively studied. This study is performed to realize a computer that starts at once in a used state and decreases the power consumption to nearly zero in a waiting state, that is, a so-called “instant-on computer.” For this reason, a memory element of the non-volatile semiconductor storage device needs to satisfy the following conditions: (1) the switching speed being less than 50 ns and (2) a rewrite count being more than 1016, which are technology specifications required for the DRAM. The lower limit (1016) of the rewrite count that is exemplified in the technology specifications is a numerical value that is defined on the basis of an access count of when access is repeatedly executed every 30 ns during ten years. When the non-volatile semiconductor storage device is used as the main memory, a refresh cycle is not needed. Therefore, the non-volatile semiconductor storage device can be used for the same purpose as the current DRAM, even when the rewrite count is a rewrite count less than the above rewrite count.
As candidates of this next-generation non-volatile semiconductor storage device, non-volatile memory elements based on various principles, such as a ferroelectric random-access memory (FeRAM), a magnetic random-access memory (MRAM), and a phase-change random-access memory (PRAM), are studied and developed. However, as candidates of a memory element that replaces the DRAM and satisfies the above technology specification, the MRAM that uses a magnetoresistance element as a memory element has great promise. Hereinafter, the memory element using the magnetoresistance element is called a “magnetic memory element.” Although the MRAM is on trial, the MRAM already achieves rewrite count performance of 1012 or more and the switching speed thereof is also the high speed less than 10 ns. Therefore, as compared with the other non-volatile semiconductor storage devices, realizable possibility of the MRAM is high.
A first problem of the MRAM is that an area occupied by one memory cell (cell area) is large, increasing a bit cost. Specifically, the currently commercialized MRAM that has the small capacity of about 4 Mbits is of a current magnetic field rewrite type. If a minimum processing dimension of a manufacturing process is set to F, the cell area becomes 20 to 30 F2 or more. As a result, it is difficult to miniaturize the cell. In the MRAM of the current magnetic field rewrite type, when the cell area is configured to be small, a reverse magnetic field (that is, minimum value as an external magnetic field to reverse magnetization) may be increased, and a current value needed for reverse may be increased as the cells are miniaturized by increasing an integration degree. For this reason, it is unrealistic to replace the DRAM by the MRAM of the current magnetic field rewrite type.
In order to change this situation, two technologies that become a breakthrough are suggested. One is a method using a Magnetic Tunnel Junction (MTJ) using an MgO tunnel insulating film. If this method is used, a magnetoresistance ratio of 200% or more can be easily obtained (refer to D. D. Djayaprawira et al., “230% room-temperature magnetoresistance in CoFeB/MgO/CoFeB magnetic tunnel junctions,” 092502, Applied Physics Letters, Vol. 86, 2005). The other is a current-injection magnetization reversal method. In particular, in the current-injection magnetization reversal method, principled difficulty with respect to miniaturization such as the increase in the reversal magnetic field according to the miniaturization of the cells, is not generated. If the cells are miniaturized, the current necessary for the magnetization reversal can be decreased according to a scaling rule, and write energy can be decreased according to the miniaturization. Since the configuration of the memory cell using one transistor per magnetic tunnel junction (MTJ) is enabled by the current-injection magnetization reversal method, it is predicted that the cell area can become 6 to 8 F2 ideally, that is, a cell area equal to the cell area of the DRAM (refer to J. Hayakawa et al., “Current-induced magnetization switching in MgO barrier based magnetic tunnel junctions with CoFeB/Ru/CoFeB synthetic ferromagnetic free layer,” Japanese Journal of Applied Physics, Vol. 45, L1057-L1060, 2006). Hereinafter, the configuration of the memory cell using one transistor per magnetic tunnel junction (MTJ) is called “1 transistor-1 MTJ configuration.” The configuration of the memory cell (“1 diode-1 MTJ configuration”) that aims at achieving a small cell area (4 F2 or less) equal to a cell area of a flash memory and uses one diode per MTJ is also suggested (refer to Japanese Patent Application Laid-Open (JP-A) No. 2004-179483). In an element where a driving layer whose magnetization direction is almost fixed to a stack direction is provided, by using only one current polarity, two kinds of transistors are decreased to one kind of transistor to simplify a circuit. By realizing a circuit of 1 transistor-1 MTJ, the cell size is decreased to become the same cell size as that of the DRAM (refer to Japanese Patent Application Laid-Open (JP-A) No. 2006-128579.
However, according to the 1 diode-1 MTJ configuration that is disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2004-179483, switching is performed by currents of both directions of a forward bias and a backward bias through the diode. That is, the switching is performed by a current (forward current) in the forward bias and a leak current in the reverse bias. For this reason, there is no change in the principle of the switching being performed by the polarity of the current. In this case, the diode is originally formed to execute selection of the MTJ in write, erase, and read operations without disturbance (crosstalk), and the leak current flows in the forward direction as well as the reverse direction. According to the above configuration that uses the operation principle of the switching being generated by the leak current in the reverse bias, the current sufficient for the switching may flow at the time of the low voltage of the forward bias. For this reason, in the operation principle, an effect of preventing disturbance becomes insufficient. That is, when the switching can be performed by the leak current of the reverse bias, the current flows at the time of the low voltage in the forward bias, and the same problem of disturbance as a simple matrix type memory that has no element selection switch cannot be avoided. For this reason, a high-integration element cannot be realized. As such, in order to realize a cross point type memory based on the 1 diode-1 MTJ configuration having a minimum cell area of 4 F2, the current-injection magnetization reversal method that uses the operation principle of the switching based on the polarity of the current cannot be adopted.
According to the configuration disclosed in Japanese Patent Application Laid-Open (JP-A) No. 2006-128579, that is, the 1 transistor-1 MTJ configuration using the element where the driving layer whose magnetization direction is almost fixed to the stack direction is provided, the switching is performed by inducing spin precession (precession motion) by spin injection from the driving layer to the free layer. However, in the operation principle of the spin precession being induced by the spin injection from the driving layer, the magnetization arrangement (combination of the magnetization directions) where magnetization directions of the free layer (storage layer) and the pinned layer (magnetization fixing layer) are parallel or anti-parallel may be deviated to one of parallel arrangement and anti-parallel arrangement. According to this configuration, the magnetization direction of the pinned layer (magnetization fixed layer) may be changed, and reliability may be lowered, when a rewrite count equal to that of the DRAM is realized. For this reason, it is difficult to realize the 1 transistor-1 MTJ configuration where the switching is performed using only the polarity of the current.